These tools grew out of our own FPGA practice — the generators we reach for on client work. We're bringing them to the web one at a time, so this is honest early access: some run in your browser today, others are command-line or still on the way.
Our AXI4-Lite register-map generator. Describe your registers once and get a synthesizable VHDL entity and package, matching C headers, and HTML documentation — from a single source of truth. Run it in the browser, or bring the command-line tool into your build.
The generator in your browser — build a register-map project and generate a reviewable bundle without installing anything.
The same generator as a command-line tool, built for professional flows:
Generate VHDL look-up tables from a math function — sqrt,
log, sin and friends — with fixed-point control over
range, width and quantization.
Run a free numerical analysis today to see the approximation error before you commit any VHDL. Synthesizable LUT generation is a paid step, coming soon.
SeriCraft — our UART interface generator, in internal use today; a web version is on the roadmap.
RegiCraft is ready to try in your browser, LutCraft's free analysis is live, and the CLI slots into professional build flows. Tell us what you're building and we'll help you fit them in. Need custom development or integration? See our Design Services.
Talk to us