AURIG Lint
A VHDL lint engine and CLI with configurable rules for naming, library policy, synthesizability, and documentation, reporting as text, JSON, Markdown, or HTML.
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Open source from LogiMentor. AURIG is our FPGA tooling stack: parsing, linting, documentation, builds, and pipeline orchestration, each piece usable on its own. Alongside it we publish reusable VHDL and Python libraries from our consulting work. Everything here is Apache-2.0.
Five tools that work on their own and compose into a pipeline. Apache-2.0, early access.
5 projects
A VHDL lint engine and CLI with configurable rules for naming, library policy, synthesizability, and documentation, reporting as text, JSON, Markdown, or HTML.
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Generates browsable documentation from VHDL, for a single file or a whole project, as Markdown or self-contained HTML.
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FPGA project automation: one YAML file drives synthesis, implementation, bitstream, and simulation across Vivado, Quartus, Diamond, and Radiant.
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An on-premise pipeline orchestrator for FPGA teams: per-project YAML, scheduled unattended runs, logs and artifacts bundled per run.
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The shared Tcl foundation of the AURIG stack: a VHDL parser that turns source into a queryable dictionary, plus project utilities and the canonical manifest schema.
View details →Reusable building blocks from our FPGA design work.
3 projects
Fixed-point arithmetic for FPGA — a synthesizable VHDL building block for DSP and math datapaths, with a Python reference model verified bit-for-bit against fxpmath.
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Floating-point arithmetic for FPGA in VHDL, using IEEE-754 field conventions — vendor-independent RTL you can inspect, verify, and carry across FPGA families.
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Vendor-independent VHDL utility library — counters, delays, CDC, CRC, arbiters, and sizing helpers, hardened across 20 years of real FPGA designs.
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